SystemVerilog for Design and Verification Online Course

Master the methodologies to verify VLSI designs. This course will enrich the fundamentals of SystemVerilog and UVM methodologies. Learn effective verification methods by utilizing OOPs, randomization and functional coverage aspects of SystemVerilog. Learn to Verify, simulate, analyse hardware description languages to the fullest.

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Learn through our Scientifically Designed & Proven 5 Step Practice Oriented Learning Process
SystemVerilog for Design and Verification Online Course
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About the Course

VLSI systems are designed using hardware description languages (HDLs). There are three types of HDLs: VHDL, Verilog, and SystemVerilog. VHDL and Verilog are considered as a general-purpose digital design language and SystemVerilog is an enhanced version of Verilog, used only for verification purpose. This course covers UVM methodology which is an advanced verification concept and gives you an in-depth introduction to the main enhancements that SystemVerilog offers for testbench development. It also discusses the benefits and issues with new features, demonstrates how verification is more efficiently and effectively done using SystemVerilog constructs, opportunity to explore in depth verification enhancements such as object-oriented design, constraint random generation, and functional coverage. At the completion of this course you should have learnt to create test plan and development with hands-on labs using the verification concepts and methodology.

Course Objectives

Upon successful completion of the course, the learner will be able to

  • Understand logic verification using Verilog simulation.

  • Explore the new features of SystemVerilog and UVM based verification and demonstrate the improvements in verification environment efficiency from their use.

  • Illustrate how to exploit these features for more efficient verification and testbench development.

  • Know the difference between synthesizable and non-synthesizable code.

  • Understand the difference between Designing and Verification of an IC.

  • Understand the differences between simulator algorithms.

  • Explain key features for verification methodologies, using some of the key features such as classes, OOP, randomization, and functional coverage.

Course Content
You will Learn through our Scientifically Designed & Proven 5 Step Practice Oriented Learning Process
iLearn
In this session, you will find video lectures and other resources to learn the concepts.
iDesign
In this session, you will start designing and creating your own programs.
iExplore
In this session, you will find interesting set of activities which will make you explore more on the specific topic.
iAssess
In this session, you will have activities to self assess your knowledge and skills on the specific topic.
iAnalyse
In this session, you will find varieties of exercises to improve your code analysis, testing and debugging skills.
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Harihara Budra P, XII std

Harihara Budra P, XII std
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