Advanced Logic Design – The Easiest Way of Learning

Develop a deep understanding of Verilog in the advanced design and analysis of digital circuits. The primary goal is to provide in depth understanding of logic and system design, synthesis, and optimization for area, speed and power consumption. The course enables the user to apply their knowledge in the design of advanced digital hardware systems.

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Learn through our Scientifically Designed & Proven 5 Step Practice Oriented Learning Process
Advanced Logic Design – The Easiest Way of Learning
  • 3 Hrs of lecture Videos
  • 13 hands-on practice exercises
  • 136 knowledge based questions
  • Lifetime access
  • Course Completion Certificate
Value Additions
About the Course

This course provides the advanced techniques in the field of designing and analyzing the digital systems via hardware description languages, combinational and sequential logic synthesis and optimization methods, partitioning, mapping to regular structures and so on.It provides ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability.One can develop skills in evaluating different data structures for target applications through this course.

Course Objectives

Upon successful completion of the course, the learner will be able to

  • Design a basic building block using Verilog HDL

  • Design logic to meet specifications

  • Learn circuit concepts to program the logic Verilog language

  • Learn advanced techniques for logic circuit optimization

  • Understand merits and limitations of logic synthesis

  • Be capable of doing advanced VHDL designs

  • Ability to use the techniques, skills, and modern engineering tools

  • Ability to apply knowledge of mathematics, science, and engineering

  • Learn to develop advanced designs such as Arbitration, streaming and packet interfacing and further about Multiclock designs and timing concepts.

Course Content
Message Interface

In this module, We will learn about the Message Interface which is a process of message passing to communicate with devices. The interface has a streaming message on one side and a simple parallel data interface on the other side. The message comes in serial manner which is send through the parallel interface.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
Clock Generation

In this module, you will learn about generating clock cycles with varying duty cycle. Counters are used to generate a clock with varying frequency and duty cycle.
You will learn about generating a divide by 2 clock, divide by 4 etc.

  • 1 Videos
  • 2 Hrs 15 Mins
  • 20 Problems
Packet Switching

In this module, we will learn about designing an interface which can be used to decode and store the correct amount of data of the incoming packet of data, which has variable length of data present within it

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
Packet boundary detection

In this module, you will learn about data packet, its importance and the need for packet boundary detection while transmitting data packets through wireless communication.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
Single Cycle Processor

In this module, you will learn about designing a Single Cycle Processor. You will also learn about Accumulator, Program Counter, ALU in a processor.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
Shift and Add Multiplier

In this module, you will learn about designing a Shift and Add Multiplier. You will learn about modeling a design with data path and control path designs.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 17 Problems
Load counter

In this module, you will learn about Load counter. Basically, you will be knowing designs 2,3,4 - bit counters. Here, you are going to load a initial value to the counter and starts counting from that loaded value.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
Register Access Interface

In this module, we will learn to design a register interface, which can access data from a source (eg. memory interface) through an exchange of predetermined signals called handshaking. Data is accessed only after the connection is established when both devices are ready.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
FIFO Design

In this module, we will learn about Multiclock FIFO which is also known as Asynchronous FIFO is a memory queue with control logic that perform read and write operation with different clock domain for both reading and writing data. It is used where two clock domains are asynchronous to each other.

  • 1 Videos
  • 1 Hrs 15 Mins
  • 16 Problems
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You will Learn through our Scientifically Designed & Proven 5 Step Practice Oriented Learning Process
In this session, you will find video lectures and other resources to learn the concepts.
In this session, you will start designing and creating your own programs.
In this session, you will find interesting set of activities which will make you explore more on the specific topic.
In this session, you will have activities to self assess your knowledge and skills on the specific topic.
In this session, you will find varieties of exercises to improve your code analysis, testing and debugging skills.
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Harihara Budra P, XII std

Harihara Budra P, XII std