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ABOUT THE COURSEThis course helps you to understand the concepts of Verilog HDL & Logic Design.This course provides an introduction to logic design and the basic building blocks used in digital systems. It starts with a discussion of combinational logic: logic gates, minimization techniques, arithmetic circuits, and modern logic devices such as field programmable logic gates.
COURSE OBJECTIVESUpon successful completion of the course, the learner will be able to:
Welcome! In this module you will be introduced to one of the basic elements of any digital system logic gates. You will be learning about the different logic gates that are available. You will learn about Gate level modeling.
In this module you will learn to design some of the basic combinational designs such as half adder,full adder. You will also learn behavioral and dataflow modeling.
In this module you will learn about basic combinational circuit like parity generator and Checker,MUX etc. You will also learn to solve some of the real time problems.
In this module you will learn about code converters and how to design them in Verilog HDL.
In this module you will learn about some of the verilog specific construct and design guidelines for designing a combinational circuit. You will also learn to solve some of the real time problems.
Sequential circuits are those that uses a clock to work. So far the designs we have been working does not require any clock to trigger. In this module you will learn about flip flops and how to write HDL code for them.
In this module you will learn a little more deep in sequential designs. Counters and Shift registers form an integral part in any digital system. You will also learn about blocking and non-blocking assignment.
A finite state machine (sometimes called a finite state automaton) is a computation model that can be implemented with hardware or software and can be used to simulate sequential logic. In this module you will learn about how to model a state machine and its types.
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