e-box vlsi academy

Marathahalli, Bengaluru. Ph.: +91 9597074313

VLSI Industry Readiness Programme Logic Design , Verification and Physical Design

  • Goal is to Make Students Industry ready
  • Understand Industry Terminologies
  • Comfortable in Handling FPGA boards
  • Develop and verify basic design

Skill Development Timeline

1 Year

  • Medium Complexity Logic Design
  • Advanced Timing concepts
  • Independently handling FPGA designs

Design Stream

  • OVM Concepts
  • System Verilog Concepts
  • Coverage concepts

Verification Stream

6 Months

  • Low Complexity Logic Design
  • Modular Testbench development for a 10K IP
  • Basic Timing concepts

3 Months

  • Verilog Coding
  • Basic Testbench Concepts


  • RLC Circuits
  • Digitial Logic (Flops, Gates, FSM, Karnaugh Map reduction)
  • CMOS Circuit Design

Current Skill Level (Bachelors/Masters)

GAP of 6 Months

  • SOC Integration, DFT concepts
  • HW-FW Co-designs
  • Backend Concepts
  • High Complexity Designs (20K+ LUTs)
  • Domain Specialization
  • Independently evolve a TB architecture for a 50K design
  • Full IP verification ownership
  • Backend Concepts
  • Coverage concepts
  • Power estimation
  • Complex Interface Designs (DDR, SERDES)
  • Medium Complexity, High speed FPGA designs (5K+ LUTs, 200mhz+)

Design Stream

  • OVM Concepts
  • System Verilog Assertions
  • Coverage concepts
  • Randomization

Verification Stream

  • Medium complexity Logic Design (Multi-clock designs, Pipelined Designs, RAM based designs)
  • Modular Testbench Concepts
  • Advanced Timing Concepts
  • Handling Low complexity FPGA design
  • Verilog Coding
  • Basic Timing concepts
  • Basic Verilog based Logic Design (Timers, FSMs)
  • Basic Testbench Concepts
  • FPGA Basics

Industry Expectation

VLSI Programme courses

Course Days Topics Covered
Circuit Theory 2 Logic Gates, Flops, Optimization
Verilog 2 Verilog constructs, Developing code in Verilog
Logic Design 3 Blocking/Non-Blocking, Clock/Resets, Timing Concepts (Setup/Hold, Max-Frequency,Clock Skew, IO Timing)
Verification 2 Basics of Testbench development Using Verilog
FPGA Design 5 Basics of FPGA, Hands on exercises
Course Days Topics Covered
System Verilog 3 Language constructs, Practical examples, Assertions
UVM methodology 4 Agent, Interface, Transactor, Sequences, Interface Scalable Testbench Development Methodology
Assertion 2 Assertion for Design, Assertion for Features using System Verilog
Coverage driven Verification 3 Randomization, Coverage measurement and strategy
Hands-on 7 Multi-Port Ethernet Switch Testbench Development from Scratch
Course Days Topics Covered
Multi-clock Design 3 Synchronization Methods, Multi-clock FIFO design
ASIC Design 4 ASIC specific design guidelines, Design for Manufacturability, Clock/Reset Strategy, Die size estimation
Linting 3 Common Design Mistakes, Understanding Lint Errors/Warnings and fixing them
Timing Closure 3 STA, Analyzing Timing reports, Fixing Timing issues – Design based/Tool based
Area Optimisation 2 Area reduction Methods, RAM based optimization, Using FPGA hard Macros
Hands-On 7 Developing a 4-port Ethernet Switch with FW interface and validating on board
Course Days Topics Covered
Die size estimation 2 Logic/RAM/Hard Macro area estimation, Area/IO limited
Floor Planning 4 Floor-planning Strategy, Using the tool, Handling Hard Macros
Equivalence Check 3 Equivalence check concept, Understanding and Fixing errors
Clock/Reset Tree Synthesis 2 Clock/Reset Strategy
STA 3 Strategies for Fixing Timing Errors using the tool
Power Estimation 2 Power Libraries, Running test for Power estimation
ECO flow 2 Estimating changes for ECO, Performing ECO changes and doing Equivalence Checks
GDS II generation 2

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