Indian Engineering Education to be FREE from March 15, 2019
ABOUT THE COURSEVLSI systems are designed using hardware description languages (HDLs). There are three types of HDLs: VHDL, Verilog, and SystemVerilog. VHDL and Verilog are considered as a general-purpose digital design language and SystemVerilog is an enhanced version of Verilog, used only for verification purpose. This course covers UVM methodology which is an advanced verification concept and gives you an in-depth introduction to the main enhancements that SystemVerilog offers for testbench development. It also discusses the benefits and issues with new features, demonstrates how verification is more efficiently and effectively done using SystemVerilog constructs, opportunity to explore in depth verification enhancements such as object-oriented design, constraint random generation, and functional coverage. At the completion of this course you should have learnt to create test plan and development with hands-on labs using the verification concepts and methodology.
COURSE OBJECTIVESUpon successful completion of the course, the learner will be able to :
In this module, you will learn about how you can access a register write and read data. You need to verify data integrity while reading it and also detect errors in the design.
In this module, you will learn about how different packets from one port can be sent to any one of the output port (i.e.) the given packet has been sent to the required output port or not.
\In this module, you will learn about the Coverage driven verification, a verification methodology in which the coverage planning precedes the rest of the verification process. You will learn about line coverage,toggle coverage,branch coverage etc.
In this module, you will learn about FIFO verification. You know how FIFO works (i.e.) how a data is stored or retrieved from a memory based on first in first out concept but here you will learn how the FIFO design needs to be verified to ensure it works in real time application. Scenarios like Overflow,Underflow need to be tested.
In this module, you will learn about the verification of round-robin arbiter where your Arbiter design is verified to ensure that the data is sent to the right location.
In this module, you will learn the strategies to write testbench for given programs using verilog.
In this module, you will learn about writing testbench to cover all the scenarios to verify message interface design.
In this module, you will learn about different kinds of assertions (Immediate and Concurrent), why assertions are used in SystemVerilog such as how Assertions are used to validate if the design is good or not and its behavior.
In this module, you will learn about UVM methodologies and how to verify testbench using them. UVM (Universal Verification Methodology) Class Library provides the building blocks to quickly develop well-constructed and reusable verification test bench components like generator/drive/monitor etc. and test environments in SystemVerilog.
In this module you will learn about hardware description language which handles all aspects of the design and verification flow and SVA(system verilog Assertions) with examples.
In this module you will learn about Task and function with certain examples using system verilog.
In this module you will learn different ways to construct testbench to cover all the scenarios to verify packet interface design with different examples.
You can opt for the following courses once you complete your ongoing course
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