# VLSI Track

This track aims to provide detailed knowledge in VLSI design process starting from digital design, hardware description languages, RTI, Synthesis and Simulation, Verification, FPGA programming and Implementation. On completion of this series of courses, learners will be well trained to understand the entire logic design process and will be well equipped to take on the challenges posed by the ever demanding chip design industry.

Includes:

• 4 hours of lecture Videos
• 206 hands-on practice exercises
• 41 Assessment exercises
• 415 knowledge based questions
• 12 Live connect sessions
(Master classes)
+91 95669 33778

### Digital Systems and Logic Design with Verilog HDL

This course helps you to understand the concepts of Verilog HDL & Logic Design.This course provides an introduction to logic design and the basic building blocks used in digital systems. It starts with a discussion of combinational logic: logic gates, minimization techniques, arithmetic circuits, and modern logic devices such as field programmable logic gates.

COURSE OBJECTIVES

Upon successful completion of the course, the learner will be able to:
• Logic Gates (OR,AND,NOT,NAND,NOR,XOR,XNOR)
• Design of Combinational logic design
• Verilog HDL codes
• Types of Modeling(Gate,Behavioral,DataFlow)
• Design of Sequential Circuits
• Blocking & Non-blocking assignments
• State diagram & State Table
• Mealy & Moore Model

## Course Content

### Introduction to Logic Gates

Welcome! In this module you will be introduced to one of the basic elements of any digital system logic gates. You will be learning about the different logic gates that are available. You will learn about Gate level modeling.

• 1 Video
• 4 Hours
• 15 Problems

### Combinational Circuit Design

In this module you will learn to design some of the basic combinational designs such as half adder,full adder. You will also learn behavioral and dataflow modeling.

• 1 Video
• 4 Hours
• 10 Problems

### Combinational Circuit Design - II

In this module you will learn about basic combinational circuit like parity generator and Checker,MUX etc. You will also learn to solve some of the real time problems.

• 1 Video
• 8 Hours
• 15 Problems

### Code Converters

In this module you will learn about code converters and how to design them in Verilog HDL.

• 1 Videos
• 4 Hours
• 10 Problems

### Combinational Circuit Design - III

In this module you will learn about some of the verilog specific construct and design guidelines for designing a combinational circuit. You will also learn to solve some of the real time problems.

• 1 Videos
• 4 Hours
• 10 Problems

### Sequential Circuit Design

Sequential circuits are those that uses a clock to work. So far the designs we have been working does not require any clock to trigger. In this module you will learn about flip flops and how to write HDL code for them.

• 1 Video
• 4 Hours
• 10 Problems

### Counters and Shift Registers

In this module you will learn a little more deep in sequential designs. Counters and Shift registers form an integral part in any digital system. You will also learn about blocking and non-blocking assignment.

• 2 Videos
• 10 Hours
• 10 Problems

### Finite State Machine

A finite state machine (sometimes called a finite state automaton) is a computation model that can be implemented with hardware or software and can be used to simulate sequential logic. In this module you will learn about how to model a state machine and its types.

• 1 Video
• 6 Hours
• 7 Problems

### Advanced Logic Design – The Easiest Way of Learning

This course provides the advanced techniques in the field of designing and analyzing the digital systems via hardware description languages, combinational and sequential logic synthesis and optimization methods, partitioning, mapping to regular structures and so on.It provides ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability.One can develop skills in evaluating different data structures for target applications through this course.

COURSE OBJECTIVES

Upon successful completion of the course, the learner will be able to :
• Design a basic building block using Verilog HDL
• Design logic to meet specifications
• Learn circuit concepts to program the logic Verilog language
• Learn advanced techniques for logic circuit optimization
• Understand merits and limitations of logic synthesis
• Be capable of doing advanced VHDL designs
• Ability to use the techniques, skills, and modern engineering tools
• Ability to apply knowledge of mathematics, science, and engineering
• Learn to develop advanced designs such as Arbitration, streaming and packet interfacing and further about Multiclock designs and timing concepts.

## Course Content

### Clock Generation

In this module, you will learn about generating clock cycles with varying duty cycle. Counters are used to generate a clock with varying frequency and duty cycle. You will learn about generating a divide by 2 clock, divide by 4 etc.

• 1 Video
• 4 Hours
• 5 Problems

In this module, you will learn about Load counter. Basically, you will be knowing designs 2,3,4 - bit counters. Here, you are going to load a initial value to the counter and starts counting from that loaded value.

• 1 Video
• 3 Hours
• 1 Problems

### FIFO Design

In this module, we will learn about Multiclock FIFO which is also known as Asynchronous FIFO is a memory queue with control logic that perform read and write operation with different clock domain for both reading and writing data. It is used where two clock domains are asynchronous to each other.

• 1 Video
• 8 Hours
• 1 Problems

### Message interface

In this module, We will learn about the Message Interface which is a process of message passing program to communicate by passing messages. A message that has a streaming message on one side and a simple parallel data interface on the other side. The message comes in Serial manner which is send through the parallel interface.

• 1 Video
• 10 Hours
• 1 Problems

In this module, you will learn about designing a Shift and Add Multiplier. You will learn about modeling a design with data path and control path designs.

• 1 Video
• 6 Hours
• 1 Problems

### Register Access Interface

In this module, we will learn to design a register interface, which can access data from a source (eg. memory interface) through an exchange of predetermined signals called handshaking. Data is accessed only after the connection is established when both devices are ready.

• 1 Video
• 8 Hours
• 1 Problems

### Packet Switching

In this module, we will learn about designing an interface which can be used to decode and store the correct amount of data of the incoming packet of data, which has variable length of data present within it.

• 1 Video
• 8 Hours
• 1 Problems

### Packet boundary detection

In this module, you will learn about what is data packet and why is it important? and what is the need for packet boundary detection while transmitting data packets through wireless communication.

• 1 Video
• 12 Hours
• 1 Problems

### Single Cycle Processor

In this module, you will learn about designing a Single Cycle Processor. You will also learn about Accumulator, Program Counter, ALU in a processor.

• 1 Video
• 10 Hours
• 1 Problems

### SystemVerilog for Design and Verification Online Course

VLSI systems are designed using hardware description languages (HDLs). There are three types of HDLs: VHDL, Verilog, and SystemVerilog. VHDL and Verilog are considered as a general-purpose digital design language and SystemVerilog is an enhanced version of Verilog, used only for verification purpose. This course covers UVM methodology which is an advanced verification concept and gives you an in-depth introduction to the main enhancements that SystemVerilog offers for testbench development. It also discusses the benefits and issues with new features, demonstrates how verification is more efficiently and effectively done using SystemVerilog constructs, opportunity to explore in depth verification enhancements such as object-oriented design, constraint random generation, and functional coverage. At the completion of this course you should have learnt to create test plan and development with hands-on labs using the verification concepts and methodology.

COURSE OBJECTIVES

Upon successful completion of the course, the learner will be able to :
• Understand logic verification using Verilog simulation.
• Explore the new features of SystemVerilog and UVM based verification and demonstrate the improvements in verification environment efficiency from their use.
• Illustrate how to exploit these features for more efficient verification and testbench development.
• Know the difference between synthesizable and non-synthesizable code.
• Understand the difference between Designing and Verification of an IC.
• Understand the differences between simulator algorithms.
• Explain key features for verification methodologies, using some of the key features such as classes, OOP, randomization, and functional coverage.

## Course Content

### Register Accessing

In this module, you will learn about how you can access a register write and read data. You need to verify data integrity while reading it and also detect errors in the design.

• 1 Video
• 10 Hours
• 18 Problems

### Multi port Switch

In this module, you will learn about how different packets from one port can be sent to any one of the output port (i.e.) the given packet has been sent to the required output port or not.

• 1 Video
• 16 Hours
• 17 Problems

### Coverage Driven Verification

\In this module, you will learn about the Coverage driven verification, a verification methodology in which the coverage planning precedes the rest of the verification process. You will learn about line coverage,toggle coverage,branch coverage etc.

• 1 Video
• 8 Hours
• 17 Problems

### FIFO

In this module, you will learn about FIFO verification. You know how FIFO works (i.e.) how a data is stored or retrieved from a memory based on first in first out concept but here you will learn how the FIFO design needs to be verified to ensure it works in real time application. Scenarios like Overflow,Underflow need to be tested.

• 1 Video
• 8 Hours
• 18 Problems

### Arbitration(round robin)

In this module, you will learn about the verification of round-robin arbiter where your Arbiter design is verified to ensure that the data is sent to the right location.

• 1 Video
• 7 Hours
• 17 Problems

### Basic design verification

In this module, you will learn the strategies to write testbench for given programs using verilog.

• 1 Video
• 3 Hours
• 17 Problems

### Verifying Message Interface

In this module, you will learn about writing testbench to cover all the scenarios to verify message interface design.

• 1 Video
• 12 Hours
• 17 Problems

### Assertions

In this module, you will learn about different kinds of assertions (Immediate and Concurrent), why assertions are used in SystemVerilog such as how Assertions are used to validate if the design is good or not and its behavior.

• 1 Video
• 2 Hours
• 17 Problems

### UVM methodology

In this module, you will learn about UVM methodologies and how to verify testbench using them. UVM (Universal Verification Methodology) Class Library provides the building blocks to quickly develop well-constructed and reusable verification test bench components like generator/drive/monitor etc. and test environments in SystemVerilog.

• 1 Video
• 2 Hours
• 19 Problems

### System verilog

In this module you will learn about hardware description language which handles all aspects of the design and verification flow and SVA(system verilog Assertions) with examples.

• 1 Video
• 2 Hours
• 19 Problems

### System verilog task and functions

In this module you will learn about Task and function with certain examples using system verilog.

• 1 Video
• 3 Hours
• 19 Problems

### Verifying packet Interface

In this module you will learn different ways to construct testbench to cover all the scenarios to verify packet interface design with different examples.

• 1 Video
• 6 Hours
• 19 Problems