Indian Engineering Education to be FREE from March 15, 2019
ABOUT THE COURSEThis course provides the advanced techniques in the field of designing and analyzing the digital systems via hardware description languages, combinational and sequential logic synthesis and optimization methods, partitioning, mapping to regular structures and so on.It provides ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability.One can develop skills in evaluating different data structures for target applications through this course.
COURSE OBJECTIVESUpon successful completion of the course, the learner will be able to :
In this module, you will learn about generating clock cycles with varying duty cycle. Counters are used to generate a clock with varying frequency and duty cycle. You will learn about generating a divide by 2 clock, divide by 4 etc.
In this module, you will learn about Load counter. Basically, you will be knowing designs 2,3,4 - bit counters. Here, you are going to load a initial value to the counter and starts counting from that loaded value.
In this module, we will learn about Multiclock FIFO which is also known as Asynchronous FIFO is a memory queue with control logic that perform read and write operation with different clock domain for both reading and writing data. It is used where two clock domains are asynchronous to each other.
In this module, We will learn about the Message Interface which is a process of message passing program to communicate by passing messages. A message that has a streaming message on one side and a simple parallel data interface on the other side. The message comes in Serial manner which is send through the parallel interface.
In this module, you will learn about designing a Shift and Add Multiplier. You will learn about modeling a design with data path and control path designs.
In this module, we will learn to design a register interface, which can access data from a source (eg. memory interface) through an exchange of predetermined signals called handshaking. Data is accessed only after the connection is established when both devices are ready.
In this module, we will learn about designing an interface which can be used to decode and store the correct amount of data of the incoming packet of data, which has variable length of data present within it.
In this module, you will learn about what is data packet and why is it important? and what is the need for packet boundary detection while transmitting data packets through wireless communication.
In this module, you will learn about designing a Single Cycle Processor. You will also learn about Accumulator, Program Counter, ALU in a processor.
You can opt for the following courses once you complete your ongoing course
E-Box is a Technology Enabled Active Learning and
Assessment platform for technology and engineering
domains apart from the basic LMS components like
quizzes, assignments, lesson components.